Epson supports AI and data-center platforms to scale bandwidth without paying penalty in power, noise or design rigidity

However, as ASIC and SoC clock receivers become increasingly customized, these fixed-amplitude standards no longer provide an optimal balance between power consumption, noise performance, and signal ...
EDN

Free reference design simplifies integration of 7:1 LVDS interfaces

Lattice Semiconductor Corporation has announced the availability of a free display interface reference design that illustrates how to use the pre-engineered I/O components within its low cost ...
Design-Reuse

Free Reference Design Simplifies Integration of 7:1 LVDS Interfaces in Both the LatticeECP2 and New LatticeECP2M FPGAs

Pre-engineered I/O Components Simplify Implementation, Reduce Component Count and System Cost HILLSBORO, OR - SEPTEMBER 27, 2006 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the ...
Design-Reuse

Lattice Semiconductor and Epson Toyocom Provide Low-Cost, High Frequency Differential Reference Clock Solution

HILLSBORO, OR -- Oct 12, 2009-- Lattice Semiconductor (NASDAQ: LSCC) and Epson Toyocom Corporation today announced a low-cost reference clock solution for SERDES applications. By utilizing Lattice's ...
EDN

How to turn every FPGA LVDS pair into a complete SERDES solution

Just a couple of days ago as I pen these words, I was chatting with Bryan Hoyer from Align Engineering. After slaving away for years in their secret underground bunker, these little rapscallions have ...